Modern semiconductor packages are manufactured by forming a number of integrated circuits on a semiconductor wafer. The wafer is typically diced—cut into individual pieces—each of which is called a die. Each die includes one or more integrated circuits on one surface. This surface (often referred to as the “active surface”) includes a number of signal interface contacts called input-output (I/O) pads.
A die is typically packaged using a carrier substrate that includes solder balls suitable for attachment onto an external circuit board. The carrier substrate usually includes a core and one or more buildup layers formed on either side of the core. Each buildup layer has metallization or traces formed on a layer of dielectric material. The carrier substrate includes bond-pads for electrical interconnection with I/O pads of the die. Traces on the substrate are used to interconnect individual bond-pads with their corresponding solder balls.
A variety of bonding techniques may be used to form reliable electrical connections between I/O pads on the die and the bond-pads on the substrate. Two of the most popular techniques are wire-bonding and flip chip assembly.
In wire-bonding, the die is placed on the carrier substrate, with its active surface facing away from the carrier substrate. Wires are then bonded to I/O pads on the die at one end, and corresponding bond-pads on the substrate at the other end.
In flip chip assembly however, the active surface of the die faces the carrier substrate when the die is attached. Small amounts of solder called solder bumps are deposited on each I/O pad prior to attachment. The solder bumps are then melted to interconnect each I/O pad on the die to a corresponding bond-pad on the substrate.
I/O pads on a die may be placed anywhere over the active surface of the die. For example, in some dice, I/O pads may be distributed all over the active surface while in others the I/O pads may be restricted to near the peripheral boundaries of the die. In either case, I/O pads on a die are typically not aligned with the bond-pads on a substrate, to which they are ultimately attached. The I/O pads may also be too close to each other to allow proper solder bump formation, as is required during flip chip assembly. As a result, it is often advantageous to redistribute these original I/O pads to new pad locations (called bump-pads) that are better suited for solder bump formation. The bump-pads can then be aligned with bond-pads on a substrate and attached using solder bumps. To redistribute the original I/O pads to new bump-pad locations suitable for flip-chip bonding, a routing layer or a redistribution layer (RDL) is typically formed over the silicon wafer, or an individual die, on the active surface.
The routing layer is often formed on a thin dielectric layer, on which conductive traces are formed to interconnect each I/O pad to a corresponding bump-pad. The traces are insulated from the lower layers of the die by the dielectric material, except at the I/O pads where they interconnect. The routing layer allows I/O drivers to be placed anywhere in the die, without having to consider positions of the substrate bond-pads. I/O drivers may thus be freely placed in the die, as the redistribution layer would align the solder bumps formed on its bump-pads with bond-pads on the substrate. The use of a routing layer also simplifies the formation of substrates, and often leads to fewer buildup layers, which reduces cost.
The routing layer may include multiple layers of dielectric materials and associated traces depending on routing needs. A passivation layer is often formed over the top routing layer, to protect metal traces from exposure to air. Openings in the passivation layer expose the bump-pads.
Under bump metallization (UBM) are typically formed on the exposed bump-pads to provide low resistance electrical connections to solder bumps, for attachment to the substrate. A solder bump is typically formed on the UBM of the bump-pad for example by deposition of solder paste.
During flip-chip attachment, the solder bumps formed on the redistributed bump-pads are aligned with corresponding bond-pads in the substrate, and then reflowed or melted to form reliable electrical and mechanical contacts.
After a semiconductor die is attached to a substrate, its solder bumps are often subjected to mechanical and thermal stress during operation. Each bump-pad helps absorb much of the stress that would otherwise impact the underlying dielectric layer in the routing layer. To buffer such stress from solder bumps, each bump-pad is often made at least as large as (and often substantially larger than) its corresponding UBM.
However, this is disadvantageous as larger bump-pads reduce the area available for routing conductive traces in the routing layer, leading to a denser arrangement of traces and bump-pads which can potentially compromise signal integrity. Moreover traces that must be routed around large bump-pads may need to be made longer, which increases their resistance and capacitance. Increased resistance and capacitance on traces, often leads to voltage drops in power traces and longer propagation delays in signal traces. In addition, newer, smaller dice often require much smaller bump-pads to increase the available area for their routing needs, and often use brittle dielectric materials.
One known method for reducing bump-pad sizes is the use of Polyimide between a large UBM formed atop a small bump-pad to assist in mitigating stress that may affect dielectric layers of the die. Unfortunately however, this adds to packaging cost and may not work well with brittle dielectric layers.
Accordingly, there is a need for semiconductor die that allows an increase in the number of traces without compromising signal integrity, and protect dielectric layers against thermal and mechanical stress.